SPI_ClearRxInterruptSource(SCB_INTR_RX_NOT_EMPTY) Īdditionally, for devices PSoC 4100 BLE / PSoC 4200 BLE / PSoC 4100M / PSoC 4200M / PSoC 4200L / PSoC 4000S / PSoC 4100S / PSoC Analog Coprocessor devices, the RX and TX FIFO depth is equal to 8 bytes/words or 16 bytes. While(SPIS_SpiUartGetRxBufferSize() != 0) //read whatever is there in FIFO until it reads 0 If((SPI_GetRxInterruptSourceMasked() & SCB_INTR_RX_NOT_EMPTY ) !=0) You could implement something like below: In the present implementation, you are stalling the code in the ISR, which is not recommended. You might not actually required a 16 byte hardware buffer to do this. You have to read the bytes one by one each time the RX FIFO not empty ISR triggers. After 8 bytes are received, the hardware RX FIFO will overflow. When you set FIFO depth to 8 bytes in the component, you can't wait until you received 16 bytes in the ISR as you are currently doing. \CortexM0\ARM_GCC_541\Debug\EPR0226_Power_Control.a(SPI_TLE_SPI_UART.o): In function `SPI_TLE_SpiUartClearTxBuffer':Ĭ:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:422: undefined reference to `SPI_TLE_DisableInt'Ĭ:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:432: undefined reference to `SPI_TLE_EnableInt' \CortexM0\ARM_GCC_541\Debug\EPR0226_Power_Control.a(SPI_TLE_SPI_UART.o): In function `SPI_TLE_SpiUartClearRxBuffer':Ĭ:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:205: undefined reference to `SPI_TLE_DisableInt'Ĭ:\Users\Administrator\Documents\PSoC Creator\smartrvpanel\EPR0226_Power_Control.cydsn/Generated_Source\PSoC4/SPI_TLE_SPI_UART.c:224: undefined reference to `SPI_TLE_EnableInt' Map.\CortexM0\ARM_GCC_541\Debug/EPR0226_Power_Control.map -T Generated_Source\PSoC4\cm0gcc.ld -specs=nano.specs -Wl,-gc-sections -g -ffunction-sections -O0 -ffat-lto-objects -Wl,-end-group It is a Master that talks to a dedicated peripheral, when configuring that SPI, the dialog allows no interrupts:īut when you do a build, these instructions are in the generated source code, and have to be commented out on each clean and build There is also a second SPI in the design, which works, but generates an error during build, that must be handled, but it should not be there. We have scoped the MOSI, CLOCK and SS to the pins on the device and the signals are present. SPIS_SpiUartPutArray(Readings,CONTROL_DATA_LEN) Sending an array of A5 5A, which should be echoed back by hard code, I am not trying to hand data off, the transmit should be getting the same array, here is the call that loads the TX buffer: We have also tried active high, but no change. The scope plot show the transmission, from a CYBLE-212006-01, 16bytes, 0,0, active low CS. When configuring, the dialog defaults to the one internal interrupt unchangeable, and I do receive the interrupt, but never receive any data, nor send any data. I have an SPI slave set up on a CY8C4125AZI-473 and I am seeing some very odd behavior in both the setup controls and the SPI is not sending or receiving data. AIROC™ Wi-Fi and Wi-Fi Bluetooth Combos.
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